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Analog Devices LTspice seminars

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21st November 2018

NOTE: This event has now passed.

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09:45 – 12:30 followed by networking lunch

CENSIS, Inovo Building, 121 George Street, Glasgow G1 1RD

This is a unique opportunity to attend an Analog Devices LTspice seminar hosted in Scotland for the first time at the CENSIS Inovo Building. This event is promoted in conjunction with Anglia Components and Abercorn Electronics.

The seminar is suitable for both new and experienced users.

Delegates will learn how to construct schematics, run simulations and debug circuits thus speeding up the design process. The seminar will also cover  how to simulate many analogue circuits, run transient, ac, Fourier and Monte Carlo analysis as well as calculate efficiencies and heat dissipation. There will also be a discussion on importing third party models as well as some of the mathematical functions LTspice can offer.

A networking lunch follows the seminar will include a tour of the CENSIS IoT Centre and engineering labs.


  • Basics:
    • Constructing the schematic
    • Shortcuts
    • AC and Transient Analysis
    • Navigating the schematic and waveform windows
  • Coffee
  • Intermediate:
    • Importing 3rd Party SPICE models
    • Stepping through parameters
    • Behavioural Voltage Sources
  • Advanced:
    • Hierarchical Schematics
    • Simulator Directives for Monte Carlo analysis, noise measurement, defining functions, Fourier analysis etc…
  • Questions/Lunch/Tour

What to bring

This is not a hands-on session and you won’t need to do anything in advance or bring any equipment including a laptop with you on the day.

Apply to join us

To apply for the seminar, please email us with:

  1. Your name and contact details (email and telephone number)
  2. Job title and current employer
  3. Please let us know in a couple of sentences why you are interested in attending the seminar

CENSIS will contact you to let you know the outcome of your application.

We expect there to be lots of interest in these seminars. Due to the limited number of places, we’ll have to give priority to engineers with experience or a proven interest in this area. Unfortunately, the seminar is not suitable for current undergraduate or postgraduate students or very recent graduates.