High-end real-time FPGA debug workshop

10th October 2017

CENSIS IoT Centre Technology Seminar Series

Inovo Building, George Street, Glasgow G1 1RD

10 October 2017, 10:00am – 3:00pm

Please join CENSIS and Telexsus for a free, interactive workshop; another in the series of seminars brought to you by the CENSIS IoT Centre.

Background

The IoT Centre at CENSIS helps companies overcome many of the challenges they face in product development and allows them to fast-track the development of IoT products and services. In addition to a demonstration area and project development space, we offer regular technology seminars with high profile vendors to provide advice and guidance on how best to use their products to generate greater business efficiencies.

Who Should Attend?

The workshop is based around practical, hands on sessions, giving engineers all the knowledge they need to start debugging their own designs. It’s aimed at engineers involved in FPGA design and debug, particularly those using high-end Xilinx and Altera devices.

Regrettably the workshop is not suitable for current undergraduates or new graduates.

Background

Exostiv FPGA debug tools are enabling engineers to identify issues in their live designs which are very difficult, or almost impossible, to resolve using traditional embedded instruments.

Since the first FPGA devices appeared the methods for probing signals within an FPGA design for real-time debugging have hardly changed.  These methods, which rely on slow speed serial interfaces such as JTAG to extract the captured signals from the FPGA, simply don’t meet the debug demands of the large complex designs implemented in today’s FPGA devices.

The small window of observation provided by traditional embedded instrument solutions leaves engineers guessing which signals to scrutinise as well as which conditions to trigger upon.  FPGA designs take hours to synthesise and implement, meaning the debug ‘guessing’ process can cause serious delays to the resolution of issues and therefore to entire projects.

Exostiv offers a cost effective, easy to use solution to this issue, providing engineers with access to thousands of signals within their designs as well as over 200,000 times more capture depth than current embedded instrument solutions, plus reduced FPGA resource consumption.

Exostiv gives engineers the visibility required for debugging the complex designs implemented in todays’ mid to high-end FPGAs, including UltraScale, Kintex-7, Artix-7, Arria 10, Stratix 10 devices.

Required Kit

You will need to bring your own laptop on the day. Development boards will be provided for you to use as part of the hands-on sessions. We’ll provide refreshments and lunch.

Apply to join us

Places for this event are limited to 12 delegates and we expect there will be a lot of interest. To register your interest, email us  and provide the following information:

  1. Confirm you want to attend the ‘FPGA debug’ workshop
  2. Name and contact details (email and telephone number)
  3. Job title and current employer
  4. Please let us know in a couple of sentences why you are interested in this workshop

The deadline for applying is 20 September 2017. We will contact you by 27 September to let you know the outcome of your application. 

Please note that because of the limited number of places, we’ll have to give priority to engineers with experience or a proven interest in this area.

This is joint event from CENSIS and Telexsus and your application information may be shared with all three organisations.

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